Considering the local magnetic characteristics of surface-mounted permanent magnet (SPM) motors, the paper proposes an adaptive connecting equivalent magnetic network (ACEMN) model to accurately predict SPM motor performance. First, for modeling the magnetic field at the inclined boundary of the stator pole shoe, a diagonal hybrid permeance element covering two materials is developed. And considering the parallel magnetization of PMs, a branching calculation of the magnetomotive force source is performed inside a cross-shaped permeance of a fan-shaped mesh. Then, by analyzing the phenomenon of magnetic field line deflection at the air gap boundary, an air gap node connecting way based on adaptive conversion of connecting permeances is built. Thereby, the rotating magnetic field of the air gap can be accurately described using the different connecting permeances with variable size. To accelerate the nonlinear solution for saturated element permeability, a hybrid iterative method is used. The validity of this modeling method is verified by finite element analysis (FEA) and prototype experiments, which allows a satisfactory compromise between accuracy and calculation speed.

Summary - This paper proposes a current-fed single-stage input-parallel-output-series (IPOS) modular converter for a large-scale photovoltaic (PV) generation connected to MVDC grids, which can realize maximum power point tracking and auto-voltage-sharing by only sampling the PV voltage and current. The submodule (SM) is integrated by an interleaved parallel boost unit and a full-bridge LC series resonant unit. The simple pulse width modulation is adopted, while the drivers of different SMs are interleaved but with the same duty cycle set. Since the full-bridge LC series resonant unit operates as a DC transformer (DCX) with zero-current switching realized for all rectifier diodes, the voltage gain of SM is only related to the duty cycle of the interleaved parallel boost unit for the boost inductor current is continuous. Hence, without any SM output voltage nor input current sensors, the SMs can automatically share the output voltage by using the same duty cycle set for each SM. Moreover, the zero-voltage-switching can be realized for switches. A 1.5 kW prototype with three SMs is built to verify the converter characteristics and control strategy.

not-yet-known not-yet-known not-yet-known unknown A Memristor-controlled CMOS reconfigurable true time delay circuit is introduced in this paper. The delay circuit includes 3 stages of g m -C all pass filter delay elements connected in cascade, and memristor-based tuneable DC voltage sources. The memristor value variation changes the DC bias voltage inputs of the delay elements, and thus controls the delay time indirectly: The memristor resistance changes in analogue from 10kΩ to 17 kΩ , changing the tuneable DC voltage source output from 584mV to 711mV DC voltage and the delay from 269ps to 632ps. The delay circuit can work in a frequency range from 50MHz to 1.6GHz with gain ripple smaller than 3dB. The resolvable delay time step across the delay range is < 8.7ps, troughing at as low as 0.4ps. A delay circuit working in the MHz region is also designed to compare the performance with the GHz circuit, and a memristor programming circuit is built to change the resistance levels of memristors.

The lifespan of a converter depends on component reliability. In non-redundant designs like buck converters, a single component failure can shut down the circuit. Capacitors are more prone to failure than inductors or semiconductors. Monitoring parameters such as equivalent series resistance, rather than manual data, better assesses a converter’s useful life. This article compares two parameter estimation methods: recursive state space and non-linear least squares, with R² values and residuals analysis ensuring reliable results that closely correlate with real converter values.

The voltage controlled oscillator (VCO) with a wide tuning range and low phase noise is extensively employed in domains such as 5G, 6G, and satellite communication. This article commences with the phase noise model to conduct an analysis of the multi-core VCO. Subsequently, the mode switching technology is elucidated. On this foundation, an X-shape compact equalizing on-chip transformer design based on the inductor sharing technique is proposed. The transformer with three modes is devised to enhance the output frequency range of the VCO. Distinct from the traditional capacitive coupling, the alteration of the effective inductance value is accomplished through the coupling between the inductors to complete the regulation of the oscillation frequency range. The proposed VCO structure adopts the 40nm process, achieving a 52.02% continuous frequency tuning range from 24.7GHz to 42.2GHz. When the bias is at 10 MHz, the phase noise varies within the range of -123dBc/Hz to -132dBc/Hz, while FoM and FoMT respectively fluctuate from 177dBc/Hz to 193dBc/Hz and 191dBc/Hz to 208dBc/Hz. Both phase noise and FoM are improved and the area is only 0.057 mm2.

This article proposes a class of asymmetric 2 ×n resistor network model which contains multiple independent resistors, the study of asymmetric resistor network models is a challenge. We conducted in-depth research on this issue using the RT-V theory (Chinese Physics B, 2017, 26(9): 090503) and achieved new theoretical breakthroughs. This paper derived five original equivalent resistance formulae for this asymmetric 2 ×n circuit network, and also discusses the analytical expressions for equivalent resistance in different special cases, and several interesting results have been derived, indicating that the original resistance formula has powerful functionality. Finally, visual graphics of two types of equivalent resistances are provided using MATLAB drawing tools, which reveals the law of equivalent resistance changing with resistance variables. The research theory and technology in this article will provide a new theoretical basis for related scientific, engineering, and simulation research.

The chip industry is essential for national security and economic development, with integrated circuit (IC) reverse engineering playing a vital role in analyzing chip structures. This process involves several steps, including layer-by-layer image acquisition using scanning electron microscopy (SEM), device identification, gate net extraction, and function inference. Segmenting electrical components and metal lines from IC images is crucial for these analyses. However, traditional image segmentation methods often fail to handle the complex and variable conditions of IC images due to insufficient expert knowledge. This study introduces an improved approach, using the UNet ++ architecture and effentnet-b7 as the encoder, called the E- UNet++ model. A post-processing denoising stage is added that contains Hough circle detection and median filtering for extracting metal lines and perforations in IC images. The primary contributions of this method are: (1) it enables fully automatic detection of metal lines and vias without manual intervention, and (2) it combines E-UNet++, Hough circle detection, and median filtering in a hybrid approach to accurately locate metal lines and vias. Experimental results on over ten thousand IC images, each measuring 1024×1024 and provided by a company, show that training with just 393 images allows the E-UNet++ model to effectively segment metal lines and vias. The average intersection over union (mIoU) is 98.09% and the mean pixel accuracy (MPA) is 99.06%, surpassing the performance of existing methods.

not-yet-known not-yet-known not-yet-known unknown A variable gain amplifier (VGA) is an essential building block used in the automatic gain control (AGC) loop to provide a continuous, adjustable gain for the signal strength. To maintain the stability and consistency of the AGC loop, it is necessary to ensure that the gain of the VGA has an accurate dB-linear characteristic. This tutorial provides a detailed overview of the development of dB-linear VGAs based on differential pair structures over recent years. We categorise various VGA cells based on differential pair structures, analyse their operating principles, and explain the key features of each topology. Based on observation and extraction of the dB-linear implementation schemes used by these VGAs, we summarise three basic methods for achieving dB-linear gain control. We also discuss specific methods for realising the exponential function, using a true exponential and a mathematical approximation, and present the different types of approximation functions adopted in the works described here. Considerations in regard to the tuning range, gain error, bandwidth, linearity, process-temperature robustness, and circuit simplicity are also discussed. Finally, we draw comparisons and give perspectives for future dB-linear VGAs.

This paper presents an AI-based framework designed for learning and regenerating analog circuits from academic papers. The framework comprises four distinct modules: circuit extractor, table extractor, text extractor, and simulation executor. The circuit extractor module utilizes deep learning object detection to identify devices and their associated textual descriptions while extracting interconnections between devices. The table extractor module handles textual and image-based tables, extracting device parameters and simulation data. The text extractor module leverages Optical Character Recognition (OCR) and AI models to extract supplementary information. The simulation executor employs this information to conduct simulations and optimize circuit performance. In our experiments, our method effectively extracts multimodal circuit design information, achieving an average accuracy of up to 97% in target detection within the circuit extractor module. The improved performance during the simulation process further validates the effectiveness of our framework.

In advanced processes, Single-Inductor Multiple-Output (SIMO) DC-DC converters with battery voltage as input face serious overvoltage problems due to low MOSFET withstand voltage. To meet the needs of SIMO converter design in advanced processes, this paper first proposes a SIMO converter with an adaptive power supply buffer (APSB) and voltage-limiting techniques in 22 nm CMOS. The proposed APSB technology ensures that the driving voltage of the power stage remains unchanged under the changing power supply, solving the breakdown problem caused by low MOSFET withstand voltage and simplifying the circuit design of the power stage. The proposed voltage-limiting techniques avoid the overvoltage of the internal circuit by special voltage-limiting design for the VX2 node and output voltage during startup and steady state. The proposed SIMO is designed and validated under a 22 nm CMOS process. The input power supply range is 2.8 V-5 V, and the three output voltages are 0.8 V, 1.1 V, and 1.8 V, respectively. The maximum load for each output voltage is 250 mA. The SIMO system achieves a peak efficiency of 92.2% over the full load range.

This article proposes a high step-up, low switching voltage stress DC-DC converter based on the traditional Boost circuit, incorporating switched-capacitor (SC) and coupled-inductor (CL) techniques. The design approach of this converter involves replacing the single switch in a single-switch DC-DC converter with SC, combining CL together, and integrating the resonant boost circuit with the Boost circuit. Compared to other traditional DC-DC converters, the improved topology of the power switches in this design exhibits lower voltage stress, lower diode current stress, fewer total components, and a common ground. The working mode and steady-state analysis of the converter are provided, and the stress derivation of the components and theoretical efficiency analysis are conducted. A comparison with other DC-DC converters is also performed. Finally, experiments are conducted on a 200W DC-DC converter prototype to verify the reliability of this converter.

Addressing the sensitivity of permanent magnet synchronous motors to external disturbances, a novel sliding mode control (NSMC) strategy is proposed to suppress sliding mode jitter and enhance speed regulation performance. First, an advanced non-singular fast terminal sliding mode (ANFTSM) surface and a new adaptive power rate reaching law (NAPRRL) were developed. A new switching function replaces the conventional sign function to enhance the system’s disturbance immunity and dynamic response speed. Then, the system’s anti-interference performance was further enhanced by introducing an improved novel sliding mode observer (INSMO) for feedback compensation of the aggregate disturbance. Finally, MATLAB/Simulink simulations and experimental validations demonstrate that the NSMC control strategy exhibits superior performance in both the start-up response and load disturbance phases, with enhanced dither-resistance, rapid dynamic response, and disturbance suppression capabilities.

This Manuscript delves into a deeper understanding of the fundamental concept of electrolysis, detailing the main types of Electrolyzers and conducting a meticulous analysis of their advantages and disadvantages. Additionally, this work presents a thorough examination of DC-DC and AC-DC converters, which are crucial in applications aimed at the production of green hydrogen, illustrating their functionality and applicability in great detail. Furthermore, the manuscript explores the diversity of power electronic systems employed in the production of green hydrogen, emphasizing the critical role of converters in this context. The investigation extends to effective strategies for integrating these technologies, aiming to optimize the green hydrogen production process. This study intends to be a significant contribution to the advancement of knowledge in sustainable technologies, highlighting power electronics as a fundamental vector in electrolysis, promoting the generation of renewable energies, and reinforcing the commitment to a greener and more sustainable future.

This work describes a novel wide tuning range ring voltage controlled oscillator (RVCO) for generating six-phase signals. The proposed circuit is realized by coupling two identical three-stage single-ended inverter based RVCOs. The coupling network injects the common mode signals from one RVCO to the other one and vice versa in cross-connected manner. Three-stage RVCOs used for coupling have been configured by modifying the conventional current-starved RVCO. The proposed six-phase RVCO is optimized using an improved version of Non-dominated Sorting Genetic Algorithm III (NSGAIII). In this algorithm, sigma scaling method is used to control the selection pressure and enhance the performance of the algorithm. The proposed RVCO oscillates at 4.3 GHz. The proposed oscillator can operate from 1.65 GHz to 4.62 GHz under the supply voltage of 1.5 V. This oscillator demonstrates a wide frequency tuning range of 95 %. The proposed RVCO has been designed in 0.18 µm standard CMOS technology and the chip area is 28 × 38.5 µm 2.

In low-voltage applications using low-Q LC filters, alias-free capacitor voltage acquisition can be achieved, but synchronous capacitor voltage sampling under high-Q filters used in high-voltage applications in grid-forming converters causes some degree of distortion and results in degradation of the power supply quality. And the 1.5 beat delay inherent in this approach limits the control bandwidth, reduces the stability region, and results in an inadequate time domain response. Despite these shortcomings, this approach is widely accepted in practice. This paper concludes that sampling 2us before the synchronous instant results in almost the same distortion as synchronous sampling, however, it can improve the dynamic performance of the system. A distortion-acceptable univariate feedback voltage dual-loop active damping control topology with much reduced computational delay is proposed, which is based on an internal active damping loop using a discrete lead compensator and a proportional resonance controller in the external voltage loop.

This paper studies the influence of the gate voltage of the power amplifier (PA) on the drain current and efficiency. This study proposes a theory of controlling input non-linearity to improve the efficiency of PAs. The theoretical efficiency of the inverse Class F PA which controlling input non-linearity is from 77 to 97%. A new design method for the inverse Class F PA that reconstructs the design of the load admittance space into a region instead of a point. To verify the validity of the proposed theory, a inverse Class F PA is designed and fabricated using a commercial 10W GaN high electron mobility transistor (HEMT). Results of the measurement show a high drain efficiency (DE) of 78.5%, a output power of 41.6 dBm and a large signal gain of 12.1 dB at 1.5 GHz. The overall PA’s size is controlled at 80*50 m m 2 .

With the renewable energy continuously access to the microgrid, the microgrid itself does not have the disadvantages of the inertia of the synchronous generator in the traditional grid is increasingly apparent, for which the generalized droop control (GDC) strategy is proposed. In the normal operation of the system, GDC has the advantages of large inertia and small active power overshoot, but when subjected to external frequency perturbations, the grid-supporting inverter with large virtual inertia is prone to large transient active power overshoot and oscillation. To address this problem, the article establishes small-signal models under different perturbations based on the GDC compared with the virtual synchronous generator (VSG) and further proposes two adaptive inertia control strategies: GDC adaptive inertia (GDCAI) and adaptive inertia for operation mode switching (AIOMS). By adjusting the virtual inertia appropriately, the rate of change of frequency (RoCoF) is maintained in the set range while improving the transient performance of the system, the methods of reduce-order of the system model and control parameter design is given, to reduce the frequency fluctuation while greatly reducing the active power overshoot and improving the response speed of the system. The effectiveness of the two control strategies is verified by MATLAB/Simulink simulation and StarSim hardware-in-the-loop (HIL) experiment.

The work elucidated in this scientific article presents a novel non-isolated high gain switched capacitor (HGSC) DC-DC converter engulfed for carbon neutral energy applications. A hybrid utilization of complementary switching approach switches enables simplified control and high voltage gain of HGSC even at low duty cycle owing to the switched capacitor along with boost inductors. Further, the proposed structure also features high efficacy, reduced voltage stress and current stress on semiconductor switching devices. The proposed HGSC DC-DC converter principle of operation along with the steady-state analysis and different switching stages were discussed in detail. Small signal analysis has been performed to analyze the stability of the proposed converter, whereas an averaging technique is performed to know its dynamics performance. Furthermore, the converter is thoroughly analyzed in terms of power losses. For comparing the practical efficiency of the designed converter, non-idealities voltage gain is derived. The efficiency of the proposed converter is validated practically and extensive performance comparison is carried out with other solutions in the literature. When a supply of input voltage 20 V feed into the proposed converter. It produces an output voltage of 140 V to 240 V output. A 200W laboratory proto model is developed; accordingly conducted extensive experimental analysis to validate the feasibility of the proposed HGSC DC-DC converter topology.