Many industries, such as automotive, are undergoing substantial transformations in their underlying electrical and electronic architecture (E/E), pushing for a transition from traditional flat architectures to more decentralized and zonal systems. Moreover, this industry’s demanding constraints and regulations (e.g., ASIL D) limit the application of COTS technologies to support this shift. Seeing this gap, semiconductor designers, like Arm, have been pushing for the Armv8-R processor architecture with specific features to cover the automotive industry’s needs. Arm introduced a new Memory Protection Unit (MPU) to improve system determinism and reduce memory access latency, enhancing its applicability in critical real-time environments. In this context, the hypervisor emerges as a solution for consolidating different subsystems onto the same hardware platform, allowing the system to meet SWaP-C (Size, Weight, and Power-Cost) requirements. However, most hypervisor implementations are not designed to run on MMU-less devices. This paper describes the journey of re-designing Bao, an open-source lightweight Static Partitioning Hypervisor (SPH), to the new generation of real-time Arm processors. The core contribution focuses on leveraging the dual-stage MPU and the Armv8-R virtualization extensions to establish a predictable virtualization infrastructure. We evaluated the hypervisor’s performance on a multi-core platform based on the NXP S32Z270 SoC. Bao MMU-less demonstrated high efficiency, with less than 1% performance degradation and only a negligible increase in memory footprint. Additionally, the system exhibited a short boot time of 2.95ms, meeting a critical requirement for real-time applications, such as those used in the automotive domain.