A two-step Single Slope ADC with inter-stage calibration for CMOS image sensorsTianyu Liu1, Rensheng Shen1, Xinshuang Yu1, Yang Qu1, Kang Cao1, and Yuchun Chang1*1 School of Integrated Circuits, Dalian University of Technology, Liaoning, ChinaEmail: cyc@dlut.edu.cn.This letter introduces a novel two-step Single Slope Analog-to-Digital Converter (SS-ADC) architecture featuring high 3-bit and low 7-bit quantization stages. It reuses the programmable gain amplifier (PGA) as the Multiplying Digital-to-Analog Converter (MDAC) for residue amplification, enhancing resource efficiency. A on-demand column-level MDAC calibration mechanism without redundant bits corrects coarse quantization errors and ensures accurate residue amplification. These innovations significantly improve speed, accuracy, and robustness, achieving an SNR of 59 dB, along with DNL and INL within 1.5 LSB, which is suitable for high-performance CMOS image sensors.Introduction: The evolution of CMOS image sensors (CIS) has driven advancements in high-speed, high-resolution imaging for scientific, industrial, and consumer applications. Among CIS components, the analog-to-digital converter (ADC) is crucial for signal fidelity, speed, and performance. Single-slope ADCs (SS-ADCs) are widely used in column-parallel CIS due to its simplicity, compact design, and low power consumption [1–5]. However, traditional SS-ADC designs face challenges in speed-resolution trade-offs, and robustness against nonlinearity and mismatches, limiting their suitability for high-performance imaging [6–9]. This work introduces a novel two-step SS-ADC architecture based on pipeline ADCs. It employs a 3-bit coarse quantization stage and a 7-bit fine quantization stage, utilizing a Multiplying Digital-to-Analog Converter (MDAC) for residue amplification. The programmable gain amplifier (PGA) is reused as the MDAC, enhancing resource efficiency. The global ramp generator produces two distinct ramp slopes for each quantization stage, allowing the ADC counter to operate at its original frequency without overclocking. Furthermore, an on-demand column-level MDAC calibration method, which allows for multiple iterations, eliminates the need for redundant bits, effectively corrects coarse quantization errors, prevents MDAC output saturation, and guarantees accurate residue amplification. These innovations address the limitations of conventional SS-ADCs, delivering improved speed, accuracy, and robustness, and making the proposed design highly suitable for high-performance imaging applications.The Structure of the Target ADC: The target CMOS image sensor readout chain, as illustrated in Figure 1, comprises PGA, comparators, registers, a global ramp generator, and a global counter. The system quantization schematic is illustrated in the right half of Figure 1, where Phase T1 performs high 3-bit quantization, and Phase T2 performs low 7-bit quantization.In the reset stage of the T1 phase, the PGA amplifies the pixel voltage and forwards it to the comparator of the SS ADC for quantization. As shown in Fig. 2(a) and Fig. 2(b), the PGA operates in two stages: in Fig. 2(a), the operational amplifier functions as a unity-gain voltage buffer, providing a common-mode voltage output (VCM); in Fig. 2(b), it switches to amplification mode, where the input is a multiple of the common-mode voltage (VCM/n, with the PGA’s gain factor of n), and the output is expressed as:\begin{equation} \begin{matrix}\text{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }V_{out\_T1}=\ V_{CM}+\left(V_{pixel\_in}-\frac{V_{CM}}{n}\right)*n\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1)\\ \end{matrix}\nonumber \\ \end{equation}This operational mode ensures that the PGA ultimately outputs the amplified pixel output voltage [10–12]. The final output of the PGA is sampled onto two capacitors: one is provided to the comparator for T1 phase quantization, and the other serves as the input voltage for the first stage of the MDAC. After using the high-slope ramp for quantization in the T1 phase, a 3-bit coarse quantization output is generated, after which the PGA is reused as an MDAC to amplify the signal residue. The MDAC operates in two stages: in Fig. 2(c), corresponding to the T1 quantization phase, the MDAC input voltage equals the PGA output voltage in the (b) stage, and the operational amplifier output is reset to the lowest voltage in the ADC range, Vref2; In Fig. 2(d), corresponding to the T2 phase, the counter and ramp are reset, and the MDAC input switches to the reference voltage according to the 3-bit quantization result. Specifically, a result of 1 corresponds to the highest ADC range voltage, Vref1, while a result of 0 corresponds to Vref2. The MDAC output in this stage is expressed as:\begin{equation} V_{OUT\_T2}=\ V_{ref2}+(2^{3}-1)*((V_{OUT\_T1}-V_{ref2})-\nonumber \\ \end{equation}\begin{equation} \text{\ \ \ \ \ \ \ }\text{\ \ \ \ }\text{\ \ }\text{\ \ }\ \ \ \ \ \ (V_{ref1}\ -V_{ref2})*\sum\frac{\text{DN}}{2^{N}-1})\ \ \ \ \ \ \text{\ \ \ \ }\ \ \ \ (2)\nonumber \\ \end{equation}During the T2 quantization phase, the comparator receives the MDAC output from the (d) stage as input, which is then used to produce the 7-bit fine quantization result. The switching timing sequence is shown in Fig. 3.The Principle of Inter-Stage Calibration: Similar to pipeline ADCs, the accuracy of the preceding stage ADC output is crucial for subsequent signal processing. In the two-stage conversion process, quantization errors arise due to the asynchronous relationship between the comparator and counter, comparator offsets, and counter delays, degrading final output accuracy. According to the MDAC output in Equation (2), if the first-stage ADC output code is higher than the theoretical value, the MDAC output falls below Vref2. Conversely, if it is lower, the MDAC output may exceed Vref1, preventing proper conversion in the next stage. To ensure accurate signal transfer and minimize quantization errors, inter-stage calibration is essential, as illustrated in Fig. 4. The calibration module, consisting of registers, XOR gates, full adders, and comparators, operates during the latter half of the reset phase in the T2 stage. Two dynamic comparators monitor the MDAC output to determine if it is within the quantization range. CLK1 and CLK2, with a 45° phase difference, generate multiple pulses during the ramp reset, while the global counter starts from 0 to count the CLK1 pulses. When the MDAC output is within range, the XOR gate outputs a low level, keeping the register unchanged as DN_OLD<0:2>. If the output is abnormal, the XOR gate outputs a high level, and the register value changes with the full adder’s output [13–16].If the MDAC output exceeds Vref1, the full adder performs an addition, adding the 3-bit quantization result to the value stored in the register. Simultaneously, as the XOR output is high, the register’s clock (clk) receives a pulse generated by CLK2, and the register output updates to follow the full adder’s output. Conversely, if the MDAC output falls below Vref2, the full adder performs a subtraction. If the MDAC output remains abnormal, the register output continues to follow the full adder’s adjustments until the MDAC output normalizes. Once the MDAC output normalizes, the XOR output becomes low, and the register output will no longer change. This calibration approach, compared to traditional methods, supports stepwise adjustments until the desired accuracy is reached, without requiring additional redundant bits, ensuring no impact on the quantization time or sampling rate. Moreover, the reuse of a global counter during this phase improves resource utilization. Since each column’s condition varies, with some requiring calibration and others not, this on-demand adjustment of register values significantly enhances overall robustness. Additionally, dynamic comparators and digital circuits such as full adders have small area occupancy, meeting column-level compactness requirements while maintaining high precision [17–20].Simulation Results: The image sensor chip utilizes a 180nm CIS process, with ADC reference voltages Vref1 of 2.45 V and Vref2 of 0.45 V, providing a range of 2 V. The theoretical resolution of the ADC is 10 bits. The simulation results of the target two-step ADC are presented as follows: The dynamic performance of the ADC is illustrated in Figure 5. A sinusoidal input signal with a frequency of 47.3 Hz was employed, sampled at a frequency of 775 kHz with a total of 16,384 sampling points. The results yielded a signal-to-noise ratio (SNR) of 59.4dB, a spurious-free dynamic range (SFDR) of 67.47dB, and an effective number of bits (ENOB) of 9.57 bit.The static performance of the ADC is simulated as shown in Figure 6. The INL is approximately +0.3/-1.39 LSB, and the DNL is approximately +0.6/-0.29 LSB, both of which are less than 1.5 LSB, meeting the high-performance requirements.