This letter presents a low-distortion bootstrapped switch for improving sampling network linearity. The dynamically driven gate approach and the dynamically driven DNW (Deep N-well) technique are proposed to reduce the parasitic capacitance at crucial nodes. Simulated in a 180nm CMOS process, the proposed switch achieves a total harmonic distortion (THD) of -102.1dB at an 80MHz sampling frequency. This is an 21.4dB increase in THD, over the conventional switch.