This work proposes an energy-efficient C-2αC Charge-Sharing (CS) successive approximation register (SAR) analog-to-digital converter (ADC). Instead of scaling capacitance, binary-weighted charges are achieved by scaling the voltages at capacitor terminals using a C-2αC ladder topology with only C and 2αC capacitance values. Unlike the exponential capacitors scaling of the typical binary-weighted CS digital-to-analog converters (DACs), this approach enables linear scaling with bit number, simplifying the handling of comparator voltage offset-induced charges. During conversion, C capacitor cells are sequentially added to the comparator input for quantization in the charge domain. This structure maintains a constant input capacitance of ~2C, allowing significant energy savings from an on-chip voltage reference buffer. A 6-bit high-level model as a proof-of-concept, marking the first CS SAR ADC architecture based on a C-2αC DAC structure, to the best of the authors’ knowledge.