The researchers use high-level synthesis (HLS) to design large-scale accelerators using huge resources to accommodate complex computing applications. The latest Multi-Die FPGAs combine multiple super logic regions (SLR) on a single device to meet the enormous resource demand for high-performance computation. However, there are two challenges when implementing the large-scale hardware kernel on multi-die FPGA. The first is the non-trivial delay penalty of wires between hardware modules across multi-die boundaries. The second is the severe local congestion issues caused by local resource utilization. Furthermore, the implementation of large-scale hardware design on multi-die FPGA faces the problem of maximum achievable frequency limitation. Therefore, this paper proposes a congestion-aware frequency-boosting method, FrqBooster. It combines modules’ location and resource consumption to provide coarse-grained floorplanning optimization. Firstly, we analyze the connections between hardware modules and build optimization objectives. Secondly, we analyze the resource cost of each module in hardware design and provide a two-stage resource balance strategy combined with resource consumption to alleviate local congestion. Finally, we design a congestion-aware algorithm to complete the overall workflow for achieving higher potential performance. In the experimentation, results demonstrate that FrqBooster achieves a maximum frequency improvement of 73.15% and 81.22% on U250 and U280 platforms compared to the default implementation by Vivado, respectively. Compared to relevant works on the same samples, it achieves maximum frequency improvement of 18.32% and 33.55%, respectively.