This letter presents a design of single photon avalanche diode (SPAD) light detection and ranging (LiDAR) sensor with 128×128 pixels and 128 column-parallel time-to-analog-merged-analog-to-digital converts (TA-ADCs). Unlike the conventional TAC-based SPAD LiDAR sensor, in which the TAC and ADC are separately implemented, we proposed to merge the TAC and ADC by sharing their capacitors, thus avoiding the analog readout noise of TAC’s output buffer, improving the conversion rate, and reducing chip area. The reverse stop-start logic is employed to reduce the power of the TA-ADC. Fabricated in a 180nm CMOS process, our prototype sensor exhibits a timing resolution of 25ps, a DNL of +0.30/-0.77 LSB, an INL of +1.41/-2.20 LSB, and a total power consumption of 190mW. A flash LiDAR system based on this sensor demonstrates the function of 2D/3D imaging with 128×128 resolution, 25k inter-frame rate, and sub-centimeter ranging precision.