This paper proposes a readout scheme that utilizes a pair of differential-clocks-assisted time-to-digital converter (DCA-TDC) in CMOS image sensors (CISs). The DCA-TDC utilizes only half the number of ordinary TDC delay chain units by employing a binary-weighted search algorithm to determine the most significant bit (MSB) for fine quantization of a single-slope analog-to-digital converter (SSADC). The layout area and dynamic power introduced by the improved DCA-TDC delay chain are reduced by half compared to an ordinary TDC delay chain. The proposed SS ADC is designed and simulated using the 0.11 µm standard CMOS process. In the design environment with an analog voltage of 3.3 V, a digital voltage of 1.5 V, a clock frequency of 62.5 MHz, and a temporal resolution of 500 ps, this design is an 11-bit ADC with column-level power consumption of 65.4 µW, a row conversion time of 2.72 µs. Furthermore, it achieves an effective number of bits (ENOB) of 10.75 and a figure-of-merit (FoM) of 103.3 fJ/step. By interpolating a DCA-TDC, the quantization speed is faster than a traditional SS ADC. This scheme offers an effective solution for implementing high-frame-rate CISs.

This paper presents an in-pixel histogramming time-to-digital converter (hTDC) based on octonary search and 4-tap phase detection, aiming to improve frame rate and reduce distance error. The proposed hTDC is a 12-bit two-step converter consisting of a 6-bit coarse quantization and a 6-bit fine quantization, which achieves a time resolution of 120 ps without a GHz reference frequency and supports multiphoton counting up to 2 GHz. The proposed hTDC is designed in 0.11 μm CMOS process with an area consumption of 6900 μm 2. Timestamp sequences from a behavioral-level model are imported to the hTDC circuit for simulation verification. The post-simulation results show that the proposed hTDC achieves about 0.8% depth precision in 9-m range for short-range system design specifications and about 0.2% depth precision in 48-m range for long-range system design specifications. Under 30 klux background light conditions, the proposed hTDC can be used for SPAD-based flash LiDAR sensor to achieve a frame rate to 40 fps with 200-ps resolution in 9-m range.

Summary: This paper proposes a 1/f noise optimized correlated multiple sampling (NOCMS) technique based on differentiated sampling weights for CMOS image sensor. Transfer functions of standard CMS and NOCMS for analyzing the suppression effect of random noise respectively are derived based on the Fourier Transform theory. NOCMS shows a dramatic advantage in the suppression of 1/f noise. For implementing NOCMS, the ramp generator provides multiple sets of ramps with different slopes to quantize the reset and signal voltages. Sampling weights are increased with the decrease of ramp slopes. The last reset and first signal values are weighted more due to their potentially higher correlations. Simulation results under 110nm CMOS technology illustrate that the ADC achieves DNL of −0.80/+0.70LSB and INL of −0.70/+0.90LSB after the NOCMS operation. The input-referred random noise is 142.9µV rms under standard CMS and 120.9µV rms under NOCMS when the number of samples equals 8. The noise reduction effect is improved by 15%. NOCMS makes it possible to further reduce 1/f noise of CMOS image sensor.