In this paper, memory optimization and architectural level modifications are introduced for low power realization of the Residue Number System(RNS) with improved flexibility for EEG signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance FIR filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed LUT model which can produce the results without using any post accumulation process. The proposed RNS design makes use of inherent parallelism among residue channels and resources available of FPGA devices, the reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is formulated to design pre-computed reverse converters for different moduli sets and implemented based on FPGA as target devices. As a result, the proposed LUT-based direct computation-based post accumulation technique for RNS-based multiplication offers high-performance FIR filter architecture which can also allow configuring the elements for different frequency responses. Experimental results show the superior performance of decomposing LUT-based direct reverse conversion over all other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations.