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Data Branch Sharing Dual-Edge Explicit-Pulsed Level Converting Flip-Flops
  • +4
  • Yanyun Dai,
  • Yanfei Yang,
  • Qi Chen,
  • Faqing Gao,
  • Nan Jiang,
  • Pengjia Qi,
  • Jijun Tong
Yanyun Dai
Zhejiang Sci-Tech University
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Yanfei Yang
Zhejiang Sci-Tech University
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Qi Chen
Zhejiang Sci-Tech University
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Faqing Gao
Zhejiang Sci-Tech University
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Nan Jiang
Zhejiang Sci-Tech University
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Pengjia Qi
Zhejiang Sci-Tech University
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Jijun Tong
Zhejiang Sci-Tech University

Corresponding Author:jijuntong@zstu.edu.cn

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Abstract

Variable supply voltage-clustered voltage scaling (VS-CVS) is an effective way to decrease power consumption without compromising performance. One of the major challenges in VS-CVS design is that level converting flip-flops(LCFFs) not only need to have low power consumption but also high performance. In this paper, we propose two new structures of LCFF: the data branch sharing LCFF based on conditional charging (DBS-LCFFCC) and the data branch sharing LCFF based on precharging (DBS-LCFFP).The new structures adopt a data branch sharing scheme to improve the speed of the circuit as well as to reduce the number of transistors. Based on simulation results using HSPICE with PTM 32nm CMOS technology, the proposed LCFFs show an improvement of 19.2% to 67.2% and 41.6% to 76.3% in power-delay-product (PDP) at 50% data switching activity, respectively, compared to other advanced LCFFs.
25 May 2023Submitted to International Journal of Circuit Theory and Applications
25 May 2023Submission Checks Completed
25 May 2023Assigned to Editor
25 May 2023Review(s) Completed, Editorial Evaluation Pending
10 Jun 2023Reviewer(s) Assigned
28 Jul 2023Editorial Decision: Revise Minor
07 Aug 20231st Revision Received
15 Aug 2023Submission Checks Completed
15 Aug 2023Assigned to Editor
15 Aug 2023Review(s) Completed, Editorial Evaluation Pending
31 Aug 2023Reviewer(s) Assigned
17 Sep 2023Editorial Decision: Accept