A low-power wideband self-biased phase-locked loop (SPLL) is proposed for multi-protocol SerDes applications in this letter. With the proposed adaptive fast-locking current circuit (AFLCC), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start-up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1-3-GHz SPLL, fabricated in TSMC 28-nm CMOS process and occupies a compact 0.028mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed from a 0.9 V supply at 1 GHz frequency.