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A 1.2V High-speed Low-power Preamplifier Latch based Comparator
  • Yue feng He,
  • Guo shun Yuan
Yue feng He
Institute of Microelectronics, Chinese Academy of Sciences

Corresponding Author:1170197398@qq.com

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Guo shun Yuan
Institute of Microelectronics, Chinese Academy of Sciences
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Abstract

The power consumption of chips has emerged as a major concern with the increased integration of analog circuitry. This work focuses on a two-stage comparator based on a preamplifier with latch for successive approximation analog-to-digital converter. In order to minimize power loss and delay time, the charge steering approach was used in the design of latch as well as preamplifier. The suggested comparator is simulated in SMIC 0.18um process in comparison to the comparator without charge steering mode. The results reveal that the average power consumption is only around 22uW for varied input voltage at a supply voltage of 1.2V, which is relatively lowered by approximately 30%. Meanwhile, delay time is also reduced by about 25%.
10 Aug 2022Submitted to Electronics Letters
16 Aug 2022Submission Checks Completed
16 Aug 2022Assigned to Editor
16 Aug 2022Reviewer(s) Assigned
27 Aug 2022Review(s) Completed, Editorial Evaluation Pending
29 Aug 2022Editorial Decision: Revise Minor
10 Sep 20221st Revision Received
13 Sep 2022Submission Checks Completed
13 Sep 2022Assigned to Editor
13 Sep 2022Review(s) Completed, Editorial Evaluation Pending
13 Sep 2022Editorial Decision: Accept