High-Level Synthesis (HLS) design space exploration plays a pivotal role in electronic design automation by automatically converting high-level descriptions (e.g., C/C++/SystemC) into register-transfer level (RTL) code, significantly enhancing hardware design efficiency. However, the HLS design space remains vast and complex, involving multiple factors such as computational modules, data flow, control flow, and memory allocation, making traditional heuristic searches and experience-driven methods ineffective for efficient optimization. Conventional heuristic searches and graph neural network-based learning approaches exhibit limitations when handling heterogeneous structures. Current research predominantly focuses on homogeneous graph neural networks or statistical model-based methods, neglecting the inherent heterogeneity in HLS designs. This paper presents the first heterogeneous graph neural network (HGNN)-based prediction framework that models HLS designs as heterogeneous graphs to precisely capture complex interactions among different types of computational units, data dependencies, and optimization strategies. We design a multi-layer heterogeneous graph message-passing mechanism combined with a self-supervised learning strategy to enhance prediction accuracy and generalization capability in design space exploration. Experimental results demonstrate that our model can accurately estimate latency and resource utilization for unseen designs (i.e., novel CDFGs) within a few milliseconds.