True time delay circuits are generally realized using variable delay all-pass filters due to their flat delay-frequency response. However, they are power hungry and practically, variations in transistor characteristics and parasitic impedances result in delay variations with frequency. This paper discusses a first-order RC-low pass filter as a TTD circuit, which leverages the fact that the phase response starts changing linearly 1 decade before the pole location. The variable delay is accomplished by changing the circuit's effective impedance using the Miller effect obviating the need for varactors or variable resistors. A bandwidth extension of the delay cell is achieved using a delay correction circuit. A 4-bit TTD circuit realized by cascading 15 stages of variable delay LPFs has been designed in TSMC 65 nm CMOS technology and post-layout simulation results show that the TTD has a power consumption of 36 mW and a delay range of 400 ps with a delay variation of ±5 ps across a bandwidth of 1 GHz.