Fig. 3 (a) The circuit simulation model in PSpice. (b) The
output voltage generated by both LCLC and LCLLC structures. (c) Input DC
voltage and current for both LCLC and LCLLC structure. (d) Output AC
voltage and current. (e) Comparisons of peak output voltage with and
without transformer adjustment.
Fig. 3c illustrates the simulated input and output voltages and currents
of both structures, showing that the LCLC structure requires a 5.1 V DC
input to generate a 50.0 V AC waveform with an average power consumption
of 17.95 W, whereas the LCLLC structure achieves the same output with a
much lower average power of 5.22 W. Thus, the LCLC structure consumes
about 3.44 times more power than the LCLLC structure. Additionally, Fig.
3c indicates the LCLLC structure needs lower input power to generate the
TTFields waveform compared with the LCLC structure. Fig. 3d shows the
output AC voltage and current.
As mentioned in the Introduction, the capacitive impedance of the
patient’s head during TTFields treatment at 200 kHz ranges from 58.6 to
91.2 Ω. Fig. 3e shows the output voltage Vp for
the LCLLC structure at capacitive impedances of 60, 75, and 90 Ω. It was
observed that Vp increases as impedance rises in
the LCLLC structure. Fig. 3e shows that voltage gain varies with
different transformer inductances. Therefore, this study adjusts the
transformer inductance to stabilize the output voltage while maintaining
the LCLLC structure. For 60 Ω impedance, the transformer inductance is
set to 5 μH to achieve an output voltage above 50.0 V. With proper
transformer inductance adjustment, the output voltage remains stable
(54.0 V) across different capacitive impedances without altering the
structure.
Experimental Test on High Frequency AC Prototype
Fig. 4 shows high frequency AC prototype, consisting of full-bridge
inverter and LCLLC resonant tank. The Transistor-Transistor Logic (TTL)
trigger signal of switch was provided by the FPGA core board
(EP4CE6F17C8, Altera Corporation). The clock of 100 MHz was used to
generate the TTL signals. Each MOSFET in a full-bridge inverter was
driven by a driver circuit. In a driver circuit, the trigger signal was
received by a high-speed optocoupler chip (HCPL-7710, AVAGO
Corporation). Then, the signal was sent to a gate driver chip
(IXDN609PI, IXYS Corporation), which boosted the TTL signal voltage to
15 V, then drove the MOSFET via some auxiliary circuits. In this study,
a DC power supply employed four 3.7 V lithium batteries with a power
output of 48 Wh. The on-time of each bridge arm is set to 2.16 μ s
and the dead-time is set to 0.34 μ s. The proposed prototype is
built to verify the theoretical analysis and simulation results. The
detailed parameter selection is shown in Table 2. (In practical
applications, there inevitably exist some discrepancies in the precision
of the components).