As a generalization of the continuous-time pipeline (CTP), we present a theoretical model that can be used to analyze any conventional continuous-time (CT) analog-to-digital converter (ADC). In addition to providing a unified approach for deriving reconstruction filter coefficients, the general model enables new ADC architectures that do not fit in the framework of neither the cascaded continuous-time sigma-delta modulators (CT-Σ∆Ms), nor the CTP ADCs. As an example exploiting this design flexibility, we present a 7th order Leapfrog ADC. The aggressive 7th order filter enables a low oversampling ratio (OSR), while stability is ensured by local digital feedback with single-bit quantizers. The modular structure makes it well-suited for a programmatic design methodology, and the layout of the ADC is generated using a custom-made Python tool for analog layout compilation. Implemented in a 130nm CMOS technology, the prototype achieves a dynamic range of 82 dB with an OSR of 11, while consuming 2.5 mW from a 1.5 V supply. The resulting Schreier figure-of-merit (FOM) is 168 dB.