This letter introduces a novel two-step Single Slope Analog-to-Digital Converter (SS-ADC) architecture featuring high 3-bit and low 7-bit quantization stages. It reuses the programmable gain amplifier (PGA) as the Multiplying Digital-to-Analog Converter (MDAC) for residue amplification, enhancing resource efficiency. A on-demand column-level MDAC calibration mechanism without redundant bits corrects coarse quantization errors and ensures accurate residue amplification. These innovations significantly improve speed, accuracy, and robustness, achieving an SNR of 59 dB, along with DNL and INL within 1.5 LSB, which is suitable for high-performance CMOS image sensors.