This paper introduces a CMOS voltage reference circuit with low line sensitivity (LS) and temperature coefficient (TC) across a wide temperature range. The circuit consume relatively with low power consumption by supplying current through a current mirror structure that utilizes leakage current. The stability of the voltage reference value (Vref) is enhanced by employing a feedback structure, making the circuit more robust to variations in the supply voltage. Furthermore, the circuit produces a stable output by compensating for p-n junction leakage current across a wide temperature range. Consequently, the proposed circuit exhibits low LS over a wide temperature range. Simulations are conducted using Hspice with the TSMC 180nm process. The proposed circuit operates at Vref of 228mV at room temperature with a variation coefficient of 0.345%. It has a line sensitivity of 0.014%/V when the supply voltage varies from 0.6V to 1.8V and a temperature coefficient of 60.2ppm/°C in temperatures range from -40°C to 150°C