In this paper, design of a new three stage amplifier is inspected and presented simply through the graph space. Indeed, after changing the signal flow graph of the DACFC amplifier using graph rules and design analysis based on graph algebra, a new design example of DACFC+ is presented, which decreases the compensation capacitor or increases the phase margin compared to the DACFC amplifier. This technique simplifies the edge representing the compensation capacitor in the feedback path by using the cascade graph rule to decrease the occupied compensation capacitor chip area. It has effective and good results. After mapping the amplifier from the graph domain to the circuit domain, the DACFC+ is simulated in 0.18-μm CMOS standard technology. When the capacitive load is C L=500 pF, and the compensation capacitor is 2.4 pF at a 3.66 MHz unity gain frequency, a phase margin of 80° is obtained. The power consumption is 178 μW, and the DC gain is above 100 dB. The average slew rate of 2.74 v/us and settling time of 0.436 μs are measured when the proposed amplifier is configured in unity-gain non-inverting configuration. The amplifier is stable with a phase margin of 57° under the load capacitance of C L=1170 pF.