Fig.3 Proposed kT/C cancellation SAR ADC with presamping
The detailed operation of the proposed kT/C cancellation technique is illustrated in the following:
  1. Φ0 sampling: during Φ0 is high, the input signal is tracked on C0.
  2. Φ1 sampling: at the final stage of Φ0sampling, Φ1 turns on and the input signal is also tracked on C1. Then, Φ0 and Φ1 turns off in sequence, and the input signal is sampled on C0 and C1.
  3. Φ2 sampling: during t1 to t2, the kT/C1 noise is amplified and stored on C2, which is same as that in [4]. The difference is that there is no input signal change but only the sampled noise at the input of amplifier, because the input signal at the bottom plate of C1 is hold constantly by C0. This eliminates the issues of amplifier saturation and nonlinearity existing in [4]. Therefore, the relatively long Δt and large amplifier gain can be used to suppress the kT/C1 noise and amplifier noise, respectively.
Comparing to [4], the additional C0 sampling operation and the kT/C0 noise are introduced. Since the C0 sampling noise is not cancelled, a large-size kT/C determined C0 capacitor is required. Nevertheless, the reason abilities and merits of the proposed technique lies in the following aspects:
  1. Although a large C0 is required, a long C0 sampling time can be allocated to relax the burden of input driver. As shown in Fig. 3, all the time expect Δt can be used for C0 sampling.
  2. As with [4], the kT/C1 noise is canceled and thus small DAC can be used to reduce the load for reference buffer.
  3. Comparing to [4], this technique suffers no amplifier nonlinear issues, and thus the long Δt and large amplifier gain can be used. This further reduces the kT/C1 noise and amplifier noise, and also relaxes the requirement on amplifier bandwidth.
Circuit Implementation and Simulation results: A14-bit SAR ADC with the proposed kT/C noise cancellation is designed in a 28nm CMOS process. As shown in Fig. 4, C0 is 2.8 pF and DAC C1 is 128 fF. The gain of the amplifier is about 10. The time duration of Δt is 25% of an entire ADC cycle. In comparison, the amplifier gain is 6 and Δt is 2.5% of an ADC cycle in [4]. The increased Δt can relax the amplifier bandwidth requirement.