References
1. C.-C. Liu, C.-H. Kuo, and Y.-Z. Lin, “A 10 bit 320 MS/s low-cost SARADC for IEEE 802.11ac applications in 20 nm CMOS,” IEEE J. Solid-State Circuits , vol. 50, no. 11, pp. 2645–2654, Nov. 2015.
2. W.-H. Tseng, W.-L. Lee, C.-Y. Huang, and P.-C. Chiu, “A 12-
bit 104 MS/s SAR ADC in 28 nm CMOS for digitally-assisted
wireless transmitters,” IEEE J. Solid-State Circuits , vol. 51, no. 10,
pp. 2222–2231, Oct. 2016.
3. R. Kapusta, H. Zhu, and C. Lyden, “Sampling circuits that break the kT/C thermal noise limit,” IEEE J. Solid-State Circuits , vol. 49, no. 8, pp. 1694–1701, Aug. 2014.
4. J. Liu, X. Tang, W. Zhao, L. Shen, and N. Sun, “A 13-bit 0.005-mm2 40-MS/s SAR ADC with KT/C noise cancellation,” IEEE J. Solid-State Circuits , vol. 55, no. 12, pp. 3260–3270, Dec. 2020.
5. R. Poujois, B. Baylac, D. Barbier, and J. Ittel, “Low-level MOS transistor amplifier using storage techniques,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 16, Feb. 1973, pp. 152–153.
6. B. Razavi and B. A. Wooley, “Design techniques for high-speed, high resolution comparators,” IEEE J. Solid-State Circuits , vol. 27, no. 12, pp. 1916–1926, Dec. 1992.
7. J. Liu, et al. ”A method for effective sampling noise cancellation in SAR ADC applications.” Chinese Patent CN202311327504.X, pub. October 13, 2023.