Fig.4 Circuit implementation of the proposed SAR ADC.
Fig. 5 shows the simulated output spectrum. Operating under 1 V supply and 200 MHz sampling rate, the simulated SNDR is 75.6 dB with a 98 MHz input signal. The total power consumption is 1.56mW. This leads to a superior Schreier Figure of Merit (FoMs) of 183.7 dB. The noise and power breakdown are provided in Fig. 6. It shows that 41% of the total power is consumed by the amplifier, 12% by the DAC, 40% by digital circuits and 7% by others. The total noise is 13.7nV2, with 40% from the amplifier, 23% from kT/C0 noise, 16% from kT/C1 noise, 9% from quantization noise and 12% from others.