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\begin{document}

\title{FPGA Lab 9}


\author{Alec Aivazis}
\affil{Affiliation not available}



\date{\today}

\maketitle

\selectlanguage{english}
\begin{abstract}
Lab 9 introduced the use of memory in order to use the data in a text file to run an audio player. I was able to compile the provided circuit and send an audio file over the serial port to the FPGA which played the song. This lab was very useful in demonstrating the use of on board memory in the context of file i/o which is an extremely useful part of any digital circuit that does not do a specific task or needs to access data that is store on an external device like a hard drive.%
\end{abstract}%



\section{Introduction}

Lab 9 covered the combination of the RS232 interface with an on-board memory module in order to playback a song that was sent over the serial connection. In order to do this, I had to use the  UART decoding and timings circuit from lab 8 and connected the result of the decoding to an on-board memory block which store the information. When an 8 bit signal was finished being decoded the memory block would then play the stored song to a speaker connected to the VGA port on the FPGA. With this circuit, I was able to play the provided file called 'Chimes\_16s.txt" by copying and pasting it over the serial monitor to the FPGA.

\section{Circuits/Diagrams}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.84\columnwidth]{figures/sound1/sound1}
\caption{{This diagram shows the part of the circuit that is responsible for storing a particular song in the on board memory, as well as playing that song to the speaker. As discussed in Figure 3, when the incoming signal is finished being decoded into the 8 bit stream, the data\_ready line goes high. This tells the memory block to write to the address that given by the wraddress pins. These pins are connected to a counter which tells the memory block to write to each memory location sequentially. The lower set of counters sync the 50 MHz clock found on the FPGA and the 16kHz frequency that the song was encoded with.%
}}
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\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/io/io}
\caption{{This diagram shows the various inputs and outputs defined for the circuit. As you can see, there is only one input that corresponds to the incoming data and another for the clock. Also, the output of the UART decoder is connected to two 7-segment displays for easier tracking of the operation of the FPGA.%
}}
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\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/serial/serial}
\caption{{This diagram shows the timing and decoding associated with communication over the serial port. The first circuit allows for a reset of the timing sequence that parses the RS232 signal and uses the a not gate to clear the counter when the signal goes high which corresponds to a stop bit. As you can see, when the array of d flip-flops has written something to the final flop, the decoding is finished and the data\_ready line goes high which enables the memory functionality discussed in Diagram 1.%
}}
\end{center}
\end{figure}

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