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\begin{document}

\title{FPGA Lab 4}


\author{Alec Aivazis}
\affil{Affiliation not available}



\date{\today}

\maketitle

\selectlanguage{english}
\begin{abstract}
Lab 4 emphasized common situations that one would encounter when building complex digital circuits. The first part looked at positive edge triggers which are a very useful way of getting a short pulse to start the logic for a particular circuit without having to worry about the length of time with which the original signal is high. The second part applied this positive edge trigger in the context of a debouncing element which is an extremely useful cirtcuit when using a switch or some other imperfect interface to start your circuit. And finally, the third section illustrated the ability of quartus to design submodules that can be replicated without the need to think about the underlying logic. This capability is extremely powerful and increases the overall readability and reusability of the designs.%
\end{abstract}%



\section{Introduction}\label{sect:intro}

In section 1, I constructed a rising edge trigger and connected it to the push buttons on the FPGA. The rising edge trigger was achieved using an AND gate and a D-flop. Since the D-flop goes high on the rising edge, the delay of the AND gate lets the signal go high momentarily before the NOT causes it to go low. This enables the counter for a short time which allowed me to time the delay of the AND gate. The only real challenge in this design was figuring out a way to quickly turn off the signal after it had gone high, after some considerations, I realized any simple logic delay would work so long as it was compared to itself with an \textit{AND} gate. The D-flops are used to synchronize the input with the board's clock.

In section 2, I was instructed to design a circuit which would debounce the push-button. Since the value needed to stay constant for a particular amount of time, I needed some sort of feedback loop that would allow the output to transition to the next level when the time came. In order to do this I used the sequence debouncer submodule that was provided in the lab files. After altering the logic a bit, I was able to create a submodule that behaved as I needed and could have a third input, \textit{done}, which would tell the debouncer that it was time to transition. 

Section 3 showed me how one can create submodules in Quartus. I created two different submodules, the debouncer and the positive edge trigger, and re-implemented the circuit I designed in section 2 using them. Doing this allows me to reuse these components in future circuits which require a positive edge trigger or a debouncer, two extremely useful components of complicated circuits.

\section{Circuit Diagrams / Figures}\label{sect:cirtcuits}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/4-1/4-1}
\caption{{\label{fig:4-1}
section 1 instructed me to construct a push button counter which would increment a counter on a rising edge and display the count on a 7-segment display. The rising edge trigger was achieved using an \textit{AND} gate  and a D-flop. Since the D-flop goes high on the rising edge, the delay of the \textit{AND} gate lets the signal go high momentarily before the \textit{NOT} causes it to go low. I then connected the output of the counter to a 7 segment display (not shown).%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/4-2/4-2}
\caption{{\label{fig:4-2}
In section 2, I constructed a circuit to debounce the push-button input. By attaching the button to a state-machine with logic as shown in figure \ref{fig:state}, I was able to output the correct digital signal as well as sustain the for a redefined time. The debouncing element had an output pin which was labeled \textit{statecnt} which I hooked up to a synchronous counter. When the counter reaches its max value, it causes the \textit{done} pin on the debouncer to go high which terminates the output. I then attached it to the same positive edge trigger discussed in figure \ref{fig:4-1}.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/4-3/4-3}
\caption{{\label{fig:state}
This is the logic for the sequence debouncing state machine as described in figure \ref{fig:4-2}. As you can see, there is a "waiting" state associated with both high and low outputs which output the old value until the counting circuit has set the \textit{done} pin high, allowing the element to go back to its intended level.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/4-6/4-6}
\caption{{\label{fig:4-3}
Section 3 replaced the subcomponents of the diagram in figure \ref{fig:4-2} with submodules created in Quartus. These submodules drastically increase both code reuasbility and readability. It is much easier to understand what is happening in this circuit (debouncing both inputs and a positive edge trigger on the \textit{cin} pin of a counter). Also, the same debouncer submodule as described in figure \ref{fig:debouncer} can be used in multiple places without having to copy the logic gates themselves. For a description of the positive edge trigger see figure \ref{fig:posedg}%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/4-8/4-8}
\caption{{\label{fig:debouncer}
This is the design for the positive edge trigger submodule that I created in Quartus and added to the diagram as shown in figure \ref{fig:4-3}. As you can see it is the same setup as described in figures \ref{fig:4-2} and \ref{fig:state}.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/4-10/4-10}
\caption{{\label{fig:posedg}
This is the design for the positive edge trigger submodule that I created in Quartus and added to the diagram as shown in figure \ref{fig:4-3}. It is slightly modified from the version I implemented in Section 2 (see figure \ref{fig:4-2}) to allow for smaller dependence on gate delays.%
}}
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\end{figure}

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