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\begin{document}

\title{FPGA Lab 3}


\author{Alec Aivazis}
\affil{Affiliation not available}



\date{\today}

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\begin{abstract}
Lab 3 introduced us to digital counters, an extremely useful digital component for timing and other applications. We also covered how one can use Quartus in order to simulate the behavior of the circuit before writing it to the FPGA. The simulator is able to compute the various delays to ensure that the FPGA will perform as expected. We also covered the implementation of binary-coded decimal counters to provide a digital timer that was sensitive to hundredths of a second. The last part of this lab involved creating a 4 bit counter that incremented once a second using only elementary gates and D-flops. This lab was extremely useful in understand the implementation of various counters that can be used to output the value of a particular binary number or the time shown on a clock.%
\end{abstract}%



\section{Introduction}

Part 1 of this lab involved the implementation of a simple counter using a Quartus Megafunction. After hooking up the counter to the FPGA's onboard clock, I tested that the counter worked as intended. Then, using Quartus's simulation features, I was able to look at the individual logic states of the parts of my logic both by tying the line to an output line on the board as well as using registers which were able to provide byte level inspection at any location on the board. Using an iPhone, I was able to record the clock as it incremented. In the 10 seconds I recorded the counter, it incremented $1.99\times10^9$ times which gives the clock a period of 

$\frac{10}{1.9\times10^9} = 50.25 MHz$

Which is pretty close to the 50 MHz that is expected by the FPGA. 

After timing the clock, I simulated its performance using the Quartus simulator and verified that the counter incrememented to the right value at the right time.


The 2$^{nd}$ part of the lab involved the creation of a binary-coded decimal counter which was made out of 5 up counters with a modulus of 10 as described in Section 2.2. In order to drive the system every hundredth of a second, I connected the FPGA's CLOCK\_50 to a modulus 500000 counter whose cout went high at the desired frequency. 


Part 3 of the lab involved the creation of a 4 bit counter from elementary gates and a D flop. I did use a Quartus megafunction in order to create a modulus counter that would drive the system every second. In constructing this diagram, I needed to create a 1 bit adder without a carry-in (done with an xor and and) 1 bit multiplexer (created with an inverter) which acts as the carry-in for the counter as a whole.

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\caption{{Part 1 of this lab involved the implementation of a simple counter using a Quartus Megafunction. By attaching the 50 MHz to an upcounter I was able to display a counter that incremented every clock cycle. I verified that the circuit was performing as intended using an output (pictured below the first up counter) as well as an oboard register that was made availible to me through Quartus.%
}}
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\caption{{This is the simulation screen presented by Quartus to show specific logic values at the defined inputs and outputs. Since the output of the hexidecimal displays are not very readable, I attached a register to an onboard register in order to read the value more clearly. I also connected the counter to one of the predefined outputs and simulated the value of the outputs in the simulator to further verify the behavior of the counter.%
}}
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\caption{{Part 2 required me to construct a binary-coded decimal counter that incremented every hundredth of a second. In order to do this, I hooked up the 50 MHz clock to a counter with a modulus of 5000. It is not until the clock has performed that many cycles that a hundredth of a second has passed. By hooking the cout of the counter to the first of the modulus 10 counters. Each modulus 10 counter was hooked up to a display which showed it values. Whenever one of the counters went past 10, it incremented the next one since the cout of one is connected to the cin of another. I synchronized the counters by hooking them up to the same clock as well as the same clear line which was connected to KEY[1].%
}}
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\includegraphics[width=0.70\columnwidth]{figures/lab3-4/lab3-4}
\caption{{Part 3 instructed me to build a 4 bit counter that incremented every second using only 1 mod counter, elementary gates and a D flop. Similar to the circuit constructed in part 2, this was made by connecting the cout of a one bit counter to the cin of another to represent next leading bit. The one bit counters were created using an xor gate and an and gate as shown in figure . Hooking up the CLOCK\_50 to a counter with modulus 5000000 which passed its signal to the first counter causes the system to tick every second. 
The clear lines of the one bit counters were created using an inverter; the clear line must be low in order for the result from the counter to be passed to the D flop. By hooking up the final D flops to the same clock, I was able to create a synchronous 4 bit counter.%
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