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\begin{document}

\title{FPGA Lab 1 and 2}


\author{Alec Aivazis}
\affil{Affiliation not available}



\date{\today}

\maketitle

\selectlanguage{english}
\begin{abstract}
These labs covered the basics of implementing digital circuitry using a field-programmable gate array (FPGA). We reviewed how one builds the program in Quartus and compiles it onto the FPGA. We also reviewed how one can constructs complex circuits very easily in Quartus and show the result using a 7-segment display. This lab was very helpful in providing the necessary building blocks for future projects involving FPGAs as it showed how one can encode the necessary logic to execute a desired task.%
\end{abstract}%



\section{Introduction}
Lab 1 briefly introduced the FPGAs we will be using for the rest of the quarter. We started off by hooked up a few LEDs to switches to see that they worked as intended. When using these DIP switches, the ON position corresponded to the LED being off because we drove the LEDs with an inverter by changing the settings. Afterwards, I implemented more complicated logic using the predefined gates in Quartus. I then compiled and loaded the circuit onto the FPGA and verified that the board performed as intended by activating the switches located on the FPGA. 

Lab 2 covered two different aspects of digital circuitry: 7-segment displays and more complex gates or blocks. I began by looking at the display logic for the displays and verified it worked by activating the switches to send hexideicaml numbers to the displays to show. I then implemented a circuit to display gray code which was much faster to test since I only have to flip one at a time. Afterwards, I hooked up a few inputs to a previously defiend submodule to display the sum of two hexidecimal numbers on the display. Then, I implemented my own submodule which squared a hexidecimal number and displayed it on an array of 7-segment displays. Finally, I used Quartus's Megafunction Wizard to make a submodule that would divide a number by ten. Using 8 of them, I was able to display the circuit designed in the previous part in decimal which was much easier to debug. This lab was extremely useful in providing examples that demonstrate the necssary steps to construct more complicated circuits and provide more complicated feedback than an LED indicator.

\section{Circuits}

\subsection{Lab 1}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/1.6/1-1}
\caption{{Section 1.1 covered how one attaches a sepcific DIP switch on the FPGA to a red LED located on the same board. This was acheived by dragged a connection between the two modules in Quartus.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/1.7/1-2}
\caption{{Section 1.2 showed how one could perform the same task as in 1.1 but using an 8 bit bus instead of connecting the 8 wires by hand individually. This was achieved by clicking and dragging a "heavy" wire to connect the input and the output.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/1.9/1-3}
\caption{{Section 1.3 covered how one uses Quartus to implement various logic gates in Quartus. First I wired the first two inputs (SW[1,0]) to a NAND gate and displayed the result on the first red LED. Then, I constructed an OR gate out of NANDS and verified the logic using the second red LED on the FPGA. Afterwards, I implemented XOR logic using 4 NAND gates and hooked up the output to the third red led on the board. Finally, I used two more DIP switches to make a 4 output decoder that matched the intended truth table and verified it using 4 more LEDs on the FPGA.%
}}
\end{center}
\end{figure}

\subsection{Lab 2}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/2.6/2-1}
\caption{{Section 2.1 introduced the 7-segment display. First I had to fix a few display bugs in the logic table in Quartus. Then, I hooked up the first 4 switches to the first 7-segment display and the next 4 DIP switches to the second one on the FPGA. I then verified that the displays worked as described by the table by trying various combinations of switches and verifying that they displayed the inteded number.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/2.8/2-2}
\caption{{Section 2.2 Introduced Gray code. I hooked up the first 4 swtiches on the FPGA to a circuit which interpretted the input as Gray code and transmitted the corresponding binary to the 7-segment display in order to show the intended number. This circuit was particularly useful in showing the ease with which one can test a 7-segment display using Gray code.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/2.9/2-3}
\caption{{Section 2.3 covered how to string 4 2-bit adders in order to create a 4-bit adder. I connected the first 4 DIP switches together to form a stream I called a. I then connected the second 4 switches into a bundle labeled b. I then added the first bit of each and transmitted the result to the first 7-segment display. The cout of this operation was connected to an adder that took the second bits of the a and b bundles and added the three bits together and displayed the result in the second 7-segment display. After tying the 4 adders together, I was able to take the final cout and transmit it to another display which displayed the constant 1 and was otherwise blank.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/2.10/2-4}
\caption{{Section 2.4 introduced Quartus Megafunctions which allowed me to create a circuit which would square an 8-bit number and display the resulting 16-bit number using 4 7-segment displays. I connected the first 8 DIP switches on the FPGA to both inputs of an 8-bit multiplier. I then bundled the result in groups of 4 and displayed each using its own 7-segment display.  I also connected the input to two displays to show the number that was being squared.%
}}
\end{center}
\end{figure}\selectlanguage{english}
\begin{figure}[h!]
\begin{center}
\includegraphics[width=0.70\columnwidth]{figures/2.11/2-5}
\caption{{Section 2.5 expanded on the use of megafunctions further to perform the same function as in 2.4 but display the various values in decimal. In order to perform this, I connected the result of the squaring megafunction to a series of 5 megafunctions which divide an 8-bit input by a 4-bit number which I set to 10. I then connected the remainder of each to its own 7-segnment display to show the tens place associated with that function. I also connected the DIP switches to 2 dividing megafunctions which divide a 8-bit number by a 4-bit number and displayed the input as a decimal on the last two 7-segment displays present on the FPGA.%
}}
\end{center}
\end{figure}

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