Pulse-Width-Modulated (PWM) thermo-optic tuning in silicon photonics requires power supplies with low quiescent current, compact size, and fast PWM output voltage. However, the transient performance of conventional outputcapacitorless low-dropout regulators (OCL-LDOs) is limited by their loop bandwidth and slew rate, which prevents them from achieving fast PWM tuning. Inspired by application-specific designs (e.g., GPU, TPU, etc.) that sacrifice general performance for specific performance improvements, this paper presents a gate-switching (GS) LDO that is optimized for fast PWM tuning instead of general transient response. In the proposed design, the speed of PWM tuning is independent of the global feedback loop of the LDO and is only limited by the discharging speed of the pass transistor gate, which is accelerated through a synchronized gate discharging (SGD) block. This design has been implemented in a 65 nm standard CMOS process, occupying an active area of 2800 µm 2. With a unity-gain-frequency (UGF) of 27.8 MHz, this design achieves an average settling time of 15 ns when transitioning between zero load current and the maximum output current, significantly faster than its 1/UGF value. With a 1.2 V input voltage, it can generate a 1-MHz, 1-Vpp output voltage with a duty ratio ranging from 2.5% to 99.5% with a 50 Ω heater load.

Time-division-multiplexing clocked-analog low dropout regulator (TDM CLDO) is a new multi-channel LDO architecture that is able to reduce the total chip area by analog hardware multiplexing. It is particularly suitable for thermo-optic tuning in silicon photonics that has a low tuning power and requires a small power supply chip area. However, previous designs require a dedicated compensation capacitor for each channel. This is because, during controller switching, one node of the compensation capacitor experiences large voltage changes that prevent reliable multiplexing of the capacitor. Multiplexing the compensation capacitor is required to further reduce chip area. This paper presents a four-channel TDM CLDO using a novel Current Miller compensation with a Degenerated Resistor (CMDR) block. This CDMR block is disconnected from voltage nodes with large changes, therefore enabling reliable capacitor multiplexing. In addition, Gray-code addressing technique is adopted to reduce the crosstalk between four channels caused by clock timing errors. Implemented in a 65 nm CMOS process, this design has a total chip area of 0.0047 mm2, which is 55% smaller than the conventional solution with four identical LDOs and consumes a quiescent current of 3.1 uA per channel. Measured results show that the presented four-channel TDM CLDO can simultaneously track four 1 Vpp sinusoidal signals up to 200 kHz.

This paper presents a Gray-code addressing time division multiplexing (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between four output channels with only one compensation capacitor. We apply the Gray-code addressing strategy to reduce the crosstalk. We also apply the split-output amplifier structure to share the compensation capacitor for further chip area reduction. In addition, we introduce a lightweight local-generated supply to increase the dynamic range. Implemented in 130 nm CMOS process, this design has a total chip area of 0.056 mm2 , which is 67.5% smaller than the conventional solution with four identical LDOs. Post layout simulation results show that the presented four-channel TDM CLDO can simultaneously track four 1 Vpp sinusoidal signals at different frequencies with negligible crosstalk. This TDM CLDO is a promising solution for supplying multiple thermo-optic phase shifters (TOPSs) in silicon photonics