Width recent advances in 3D NAND flash memories and the introduction of Quad Level Cells (QLC) and Penta Level Cells (PLC), the need for on-chip negative voltage generation is becoming essential from the perspective of read window budget (RWB) enhancement and control over erase block size. Furthermore, this capability will be potentially useful for block-by-deck erase, which is becoming a mainstream feature for solid state drive customers. Negative voltage will allow users to effectively perform erase and erase verify (EV) without stringent voltage constraints currently being placed due to limited voltage range available for cell placement. In addition, negative voltage will allow users to lower source voltage and hence lower supply headroom lowering power consumption. In this paper, we discuss the usage and benefits of generating on-chip negative supply voltage to 3D NAND flash memories.