Nanoscale memristors open up new opportunities for the development of brain neural networks. Simple and precise memristors enhance the performance of various neural networks and operational circuits. In this letter, a three-terminal memristor is proposed, which makes the memristor more flexible and practical in circuit design and application through the introduction of a control port. Consid-ering that the resistance of a three-terminal memristor consists of three parts, i.e., metal region, low-resistance region, and high-resistance region, a three-segment piecewiselinear method is applied to fit these three regions. The model of this memristor is constructed through the derivation of the memristor formula and working principle. Candence simulations are conducted on the resultant circuit to verify its correctness.

Nanoscale memristors open up new opportunities for the development of brain neural networks. Simple and precise memristors enhance the performance of various neural networks and operational circuits. In this letter, a three-terminal memristor is proposed, which makes the memristor more flexible and practical in circuit design and application through the introduction of a control port. Consid-ering that the resistance of a three-terminal memristor consists of three parts, i.e., metal region, low-resistance region, and high-resistance region, a three-segment piecewiselinear method is applied to fit these three regions. The model of this memristor is constructed through the derivation of the memristor formula and working principle.Candence simulations are conducted on the resultant circuit to verify its correctness.

A three-terminal memristor model is developed in order to improve the anti-interference performance of the memristor and address the issue that the resistance value of the conventional two-terminal memristor is readily impacted by voltage. In order to simulate and validate the function of the three-terminal memristor, the logic circuit and multiplication circuit are developed using this model in this work using the cadence ic617 program. According to the findings, the three-terminal memristor multiplication circuit uses less energy than the typical conventional multiplier circuit, consuming only 0.335 uW. The memristor offers the benefits of low power consumption, compact size, and great integratability as a nanoscale device.