In this paper, A 7.2 GHz dual-core H-shaped-inductor based voltage-controlled oscillator (VCO) with single-mode oscillation is presented. The VCO utilizes a novel 6-port H-shaped structure formed by coupling two single-turn inductors, which effectively suppresses unwanted oscillation modes and enhances the quality factor (Q) of the desired mode. Furthermore, a noise compensation technique is proposed, which employs varactors to mitigate thermal noise induced by bias resistors, thereby improving the VCO’s overall performance. Implemented in a 110 nm CMOS process, the VCO consumes 39.6 mW and achieves a phase noise of -128.9 dBc/Hz at a 1 MHz frequency offset from a 7.2 GHz carrier frequency, with a corresponding figure of merit (FoM) of 190.1 dBc/Hz.

This paper presents a novel integrated temperature sensor structure that utilizes a built-in feedback loop. The structure does not require any additional references, and it embeds the successive approximation logic from the SAR ADC into the temperature sensor circuit, eliminating the need for an external analog-to-digital converter. Consequently, the proposed structure is simpler and faster in converting temperature to digital code values than conventional integrated temperature sensors. The sensor is implemented in 90 nm CMOS technology. An inaccuracy of ±0.58 °C is achieved across a temperature range of -20 °C to 100 °C. With a conversion time of 0.7 μs, the temperature sensor can convert to a digital code value in a very short period of time. Additionally, with a conversion time of 0.7 ms, a resolution of 0.18 °C is achieved.

This paper introduces a low-dropout regulator (LDO) with a quick transient response to the load and no off-chip capacitance. The LDO in this work powers digital modules in system-on-chip (SoC). It has low output voltage variation and fast recovery time during load changes. This paper proposed a novel tri-loop regulation method. The basic loop is a conventional feedback loop for LDO to ensure output voltage accuracy. The transient-enhanced loop is an improved design based on the flipped voltage follower (FVF) that compensates for the effect of removing off-chip capacitance on circuit stability. The introduced Miller capacitor is used to form the AC-coupled loop, further ensuring pole separation. It is worth mentioning that this paper introduces 2 FVFs for building basic loop and transient-enhanced loop. In addition, a bandgap reference (BGR) with a self-starting circuit is designed in this paper. The LDO described in this paper operates at 5V. The LDO is based on a 0.18 um CMOS process. The dropping and rising voltages are merely 24.5 mV and 25 mV when the load current (I load) fluctuates between 1 and 50 mA. And the corresponding settling times are 2.5 us and 1.9 us respectively. The LDO described in this paper has an output of 1.8 V and the load regulation (LDR) is as low as 6.68 uV/mA.