The Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 611731, China
E-mail: liujiaxin@uestc.edu.cn
The fully passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) are simple, OTA-free and scaling friendly. Previous passive NS-SAR ADCs rely on the multi-path-input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high-order systems. This work proposes a new fully passive NS-SAR technique, it can realize 2× gain with a simple structure, leading to the reduced comparator power and less parasitics. This technique is also easy to extend to high-order NS-SAR ADCs.
Introduction: The NS-SAR ADC is an emerging ADC architecture that aims to combine the benefits of both SAR and ΔΣ ADCs while simultaneously obviating their drawbacks [1-6]. There are three types of NS-SAR ADCs in general. The first one is to use the closed-loop operational transconductance amplifiers (OTAs) to realize the active integrators, but OTAs consume high static power [1]. The second one uses the open-loop dynamic amplifier to reduce power consumption [2]. However, the gain of dynamic amplifier is sensitive to process, voltage, and temperature (PVT) variations. The last one is the passive NS-SAR ADCs which do not consume static power and are PVT robust. Nevertheless, the passive NS-SAR ADCs also have their own limitations.
Previous passive NS SAR: In [3], the second-order NS SAR ADC samples the residual voltage on the capacitive digital-to-analog converter (CDAC) through a small residual capacitor, and then uses the sampled residue voltage to complete the first- and second-order integrations in turn. However, the small residue capacitor introduces a large kT/C noise. Besides, in order to compensate for the signal attenuations during residue sampling and passive integrations, the multi-path-input comparator needs to provide large path gains. To realize the NTF of (1-0.75z-1)2, the comparator path gain ratio needs to be 1:4:16. For the same noise budget, the comparator power consumption is 441× larger than that of a single-path-input one. The work in [4] removes the residue sampling operation, greatly reducing the kT/C noise. It also reduces the comparator path gain ratio to be 1:3:12, leading to the reduced comparator power of 256× larger than that of a single-path-input one. However, the comparator power is still too large, which often dominates the total ADC power and restricts the NS-SAR to be extended to higher-order. In [5], the integration capacitor is split into 2 parts and stacked after the integration. In theory, it can realize 2× passive gain, and therefore the comparator path ratio can be reduced by nearly half. However, the capacitor stacking causes additional signal attenuation due to the parasitics from the capacitor plates, which can be a large portion of the effective capacitor. The work in [6] uses the capacitor stacking to realize 4× passive gain, and only requires a single-path-input comparator. Also, by the differential integration, it can reduce the integration capacitors by 4× than [4] and [5]. However, it also suffers from the signal attenuation caused by the capacitor stacking, and which can be more severe than [5] because its complex switch network. Besides, it is difficult to extend this technique to higher-order NS due to the severe parasitics.
Proposed passive NS SAR with 2× gain: Inspired by the above NS SAR techniques, this paper proposes an integration circuit to achieve 2× passive gain in a simple manner. As shown in Fig. 1, the integration capacitor is split into two parts. During the integration phase, the two parts are connected in parallel between the two CDACs for differential integration, the obtained integration voltage is denoted as Vint, as shown in Fig. 1a. After integration, the bottom plates of the two parts are grounded, and therefore, the differential voltage between their top plates is obtained as 2Vint, as shown in Fig. 1b. In this way, the 2× passive gain is realized. It can be seen that the circuit is simple and does not need capacitor stacking.