Fig.2 Proposed NS SAR schematic and timing
Based on the proposed technique, a second-order NS-SAR ADC is designed,
as shown in Fig. 2. After the normal SAR conversion, the first- and
second-order differential integrations take place in run. After each
integration, the bottom plates of the integration capacitors are
grounded to realize the 2× passive gain. The top-plates of the
integration capacitors are connected to the comparator inputs. A
3-path-input comparator is used as the adder in the feedforwad path and
also provides the required gains for the integration signals. As there
is already 2× gain realized in the
passive integrator, the required comparator gains for the integration
paths can be reduced by half. To realize the NTF of
(1-0.75z-1)2, the required path gain
ratio is 1:1.5:6. For the same noise budget, the comparator power
consumption is 72.25× of that of a single-path-input one.
Table 1 summarizes the capacitor size and comparator gain ratio of this
work, and compares them with the prior work [3] and [4] for the
same kT/C noise and comparator noise budget. Both of the three works
realize the NTF of (1-0.75z-1)2. The
work [3] suffers from the significant residue sampling noise,
resulting in the large CDAC size. The work [4] obviates the residue
sampling noise, and therefore it can reduce the CDAC size by 5× and
reduce the total capacitor size by 2.4×. Comparing to [4], this work
reduces the integrator capacitor size by 4× by using the differential
integrations, and reduces the total capacitor size by 2.8×. Besides,
this work can reduce the required comparator path gains, the comparator
power of this work is 6.1× smaller than [3] and 3.5× smaller than
[4]. The reduced comparator power can significantly improve the
power efficiency of the NS-SAR ADC, and makes the higher-order NS
extension possible.
Table 1: Comparison of capacitor size and comparator power for
the same kT/C and comparator noise budget