A high speed and low power input/output buffer for time interleaving circuit is proposed in this letter. The buffer can be applied to high speed circuits operating at 20GS/s. This novel two-stage buffer is employed with bandwidth expansion and slew-rate enhanced techniques. An improved common-mode feedback circuit stabilizes the output common-mode voltage. This prototype buffer is fabricated in 45nm COMS process, and achieves 7.2bit ENOB at 10GHz input frequency with power consumption of 20.4mW, load of 0.3fF.