A new Decision-Based Adaptive Denoising Filter (DBADF) algorithm & hardware architecture are proposed for restoring the digital image that is highly corrupted with impulse noise. The proposed DBADF detects only the corrupted pixels and that pixel is restored by the noise-free median value or previous value based upon the noise density in the image. The proposed DBADF uses a 3 × 3 window initially and adaptively goes up to 7 × 7 window based on the noise corruption more than 50% by impulse noise in the current processing window. The proposed architecture was found to exhibit better visual qualitative and quantitative evaluation based on PSNR, IEF, EKI, SSIM, FOM, and error rate. The DBAMF architecture also preserves the original information of digital image with a high density of salt & pepper noise, when compared to many standard conventional algorithms. The proposed architecture has been simulated using the VIRTEX7 FPGA device and the reported maximum post place and route frequency are 149.995MHz and the dynamic power consumption is 179mW.

Ultrasound images often get distorted by impulse noise during data acquisition and processing in the Back-end of the system, which overlay the finer details of the scanned body parts. Generally, a portable low-cost USG system doesn’t have an impulse noise-cleaning module which hinders detections of smaller details in the images. A Depth Invariant Impulse Noise Removal (DIINoR) algorithm and its hardware architecture for real-time impulse noise removal from the corrupt USG image are proposed in this paper. In this decision-based algorithm, the corrupt pixel is first detected depending on the homogeneity of the processing window and is restored with the median of the window or previous pixel value. Testing of the DIINoR algorithm on different USG images establishes that the denoised images have superior quantitative performance compared to those of existing schemes. Implementation of this architecture in VIRTEX-7 FPGA gives a maximum clock frequency of 357.96 MHz. Synthesis of this architecture using UMC 90nm technology gives 103 mW power consumption at a clock frequency of 100 MHz with a gate count of 63K (NAND2) including two memory buffers which proves its suitability for the real-time fixed and random valued impulse noise cleaning in the Back-end of the portable USG system.