A low voltage two-stage rail-to-rail regenerative comparator is presented. For the first time, a thyristor-based latch is introduced in this work, enabling the comparator’s rail-to-rail operation. The proposed comparator is post-layout simulated in a standard 180nm CMOS technology. The results certify that the comparator’s delay and power are less than 28ns and 230nW with 0.6V supply voltage and 1MHz sample rate. The total input-referred offset voltage (3std+mean) is less than 6.2mV over the entire rail-to-rail common-mode voltage range. In comparison with similar works the proposed comparator has the lowest delay and offset and achieves the best FOM.