New emerging nano-scale technologies like hydrogenated noncrystalline-silicon thin-film transistors (TFTs) and memristors, fabricated at low temperatures and over large areas, permit low-cost processing and 3D integration with CMOS cores. Here, we aim to propose a mathematical model which explains the memory-TFT threshold voltage shift due to the gate bias instability. Then, based on this mathematical approach, we propose a novel learning synapse composed of a voltage/flux driven memristor in parallel with a common-source memory-TFT with a memristive load. The proposed device realizes the triplet-based spike-timing-dependent plasticity rule (TSTDP) as a more realistic form of learning than the purely pair-based STDP (PSTDP). PSTDP is a synaptic learning rule which utilizes a constant-frequency pairing protocol to induce synaptic weight change and cannot explain the modification due to the frequency changes of spike pairs, and also the outcomes of triplet and quadruplet experiments. However, TSTDP improves the learning capabilities of the conventional PSTDP and reproduces the results of more electrophysiological experiments. In this paper, we apply various spike patterns like different-frequency and different-timing spike pairs, spike triplets, and quadruplets to the proposed device. Our simulations confirm a close match with the experimental data sets of real biological synapses.