This manuscript presents a 12-bit 100-MS/s nonbinary successive approximation register (SAR)-assisted analog-to-digital converter (ADC) implemented in a 65-nm CMOS process. To achieve an optimal trade-off among conversion speed, power consumption, and chip area, this work proposes key design techniques, including a nonbinary capacitive digital-to-analog converter (CDAC) with multi-reference and Vcm-based switching, a coarse-fine comparator integrated with on-chip offset calibration, and optimized dynamic asynchronous loop (DAL) and dynamic SAR logic (DSL). Measurement results demonstrate that at 100 MS/s, the ADC achieves a peak effective number of bits (ENOB) of 10.11 bits, a peak signal-to-noise and distortion ratio (SNDR) of 62.64 dB, and a Nyquist-Walden figure of merit (FoM) of 21.87 fJ/conversion-step. The core area is merely 0.034 mm², with a total power consumption of 2.4 mW under a 1.0-V supply.