In modern communication systems, signal bandwidth continues to expand and the signal environment grows increasingly dense. Accurate extraction of narrowband target signals from wide frequency bands has thus become a key requirement in digital signal processing. Traditional serial digital down conversion (DDC) systems face real-time constraints in high-speed sampling scenarios. They struggle to adapt to the synchronous processing of multiple signals within wide frequency bands. Based on the Xilinx VU5P Field-Programmable Gate Array (FPGA), this paper designs and implements a 16-channel parallel DDC architecture. It adopts parallel mixing and polyphase filtering decimation technology to decompose 5 Gsps high-speed sampling signals into 16 channels of 312.5 Msps low-speed sub-signals. The system can synchronously process 5 MHz narrowband QPSK and 50 MHz wideband QPSK signals under dual carriers of 1 GHz and 1.1 GHz. Simulation and hardware test results indicate that its processing speed is 16 times higher than that of traditional serial architectures. The output signals are free from aliasing distortion, with stopband attenuation of no less than 60 dB and resource occupancy rate below 15%, showing promising engineering application prospects.