A Hybrid FPGA-GPU-based Hardware Accelerator for High Throughput 2D
Electrical Impedance Tomography
Abstract
A high-resolution two-dimensional (2D) electrical impedance tomography
(EIT) system requires a larger number of electrodes and a finer mesh
than its traditional counterpart. This increases the required number of
measurements and, in turn, the amount of computation for the image
reconstruction. Given the inverse and ill-posed nature of the EIT
systems, they require a high signal-to-noise ratio (SNR) acquisition
system as well as a high-precision hardware accelerator platform. In
this paper, we present a field programmable gate array (FPGA)-based
acquisition system with a tunable single-frequency current source that
can reach an acquisition speed of more than 500 and 2400 frames per
second (fps) for an excitation signal frequency of 500 kHz using 32 and
16 electrodes, respectively. The data processing and reconstruction are
carried out using the most recent embedded Graphical Processing Unit
(GPU, Nvidia Jetson Orin) by utilizing multiple Cuda cores to perform
parallel high-speed 2D image reconstruction. Five different algorithms,
namely linear back projection (LBP), Tikhonov regularization (TK),
one-step Gauss Newton (GN), Landweber (LW), and iterative Tikhonov
(ITK), were used for investigation. A gain in speed-up of at least 4
times was observed over the traditional implementations on recent
general-purpose computers (PCs). Extensive experiments indicate that the
proposed system can yield a throughput of more than 2500 fps for a
16-electrode system with around 8192 mesh elements. This paves the way
for EIT systems to be potentially used in high-speed imaging
applications as well as in 3D EIT applications which involve even larger
amount of mesh elements.