Abstract

not-yet-known not-yet-known not-yet-known unknown In this study, a comprehensive investigation of a short channel Heterojunction Hetero-Dielectric Graded Silicon-Germanium Channel Double Gate Tunnel FET (HJ-HD-GSGC-DG-TFET) is performed to justify improvement of its various Figure of Merits (FOM) in comparison to its four counterparts. A physics-based explicit analytical model for surface potential profile, drain current, and capacitance is created utilizing bandgap engineering techniques of a graded silicon-germanium channel (Si(1-x)Gex) with a pure germanium source and a lightly doped silicon drain operating at a low supply voltage (VDS) of 0.8 V in a 40 nm technology node. The effects of trap assisted tunneling, source depletion with fringing field effect, and mobile charges in intrinsic channel segments are taken into account while developing analytical models, and the results are consistent with TCAD simulations. The proposed device achieved the most important Figure of Merits (FoM) such as an increase in ON current to 3.74 x 10-4 A/ μm with a steeper subthreshold swing of 28.3 mV/decade, a low threshold voltage of 0.42 V, a moderate on-off current ratio of 109 order, a maximum transconductance of 0.82 mS, a cut off frequency of 13.52 GHz, a gain band width (GBW) of 19.8 GHz and reduced power dissipation, making the device most promising for low power integrated circuits.