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Temperature dependence of ESD effects on 28nm FD-SOI MOSFETs
  • +4
  • yiping Xiao,
  • Chaoming Liu,
  • Yanqing Zhang,
  • Chunhua Qi,
  • Guoliang Ma,
  • Tianqi Wang,
  • Mingxue Huo
yiping Xiao
Harbin Institute of Technology
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Chaoming Liu
Harbin Institute of Technology

Corresponding Author:cmliu@hit.edu.cn

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Yanqing Zhang
Harbin Institute of Technology
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Chunhua Qi
Harbin Institute of Technology
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Guoliang Ma
Harbin Institute of Technology
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Tianqi Wang
Harbin Institute of Technology
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Mingxue Huo
Harbin Institute of Technology
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Abstract

The failure mechanisms caused by electrostatic discharge (ESD) effects at ambient temperatures ranging from -75℃ to 125℃ are investigated by Silvaco TCAD simulator. The devices are NMOS transistors fabricated with 28nm fully depleted silicon-on-insulator (FDSOI) technology. Results indicate that with an increase in temperature, the first breakdown voltage of the device decreased by 27.32%, while the holding voltage decreased by approximately 8.49%. The total current density, lattice temperature, and potential etc. were extracted for a detailed insight into the failure process. These findings provide valuable references for the design and development of ESD protection devices applied at different temperature ranges.
31 Mar 2023Submitted to Engineering Reports
06 Apr 2023Submission Checks Completed
06 Apr 2023Assigned to Editor
06 Apr 2023Review(s) Completed, Editorial Evaluation Pending
10 Apr 2023Reviewer(s) Assigned
09 May 2023Editorial Decision: Revise Major
05 Jun 20231st Revision Received
06 Jun 2023Submission Checks Completed
06 Jun 2023Assigned to Editor
06 Jun 2023Review(s) Completed, Editorial Evaluation Pending
07 Jun 2023Reviewer(s) Assigned
12 Jun 2023Editorial Decision: Accept